Semiconductor device and manufacturing method thereof
US8013442B2 · kind B2 · utility
0Cited by
10References
12Claims
0Family size
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Key dates
| Filing date | Mar 21, 2008 |
| Grant date | Sep 6, 2011 |
| Priority date | — |
| Expiry date | Oct 4, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a semiconductor device according to the present invention, a plurality of opening regions 5 to 8 are formed in an insulating film on a pad electrode 3. A metal layer 9 formed on the pad electrode 3 has a plurality of concave portions 10 to 13 formed therein by covering the opening regions 5 to 8. Moreover, in a peripheral portion at a bottom of each of the concave portions 10 to 13 in the metal layer 9, the metal layer 9 and a Cu plating layer 19 react with each other. By use of this structure, the metal reaction area serves as a current path on the pad electrode 3. Thus, a resistance value on the pad electrode 3 is reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.