Patent · US Active

Integrated circuit memory with word line driving helper circuits

US8014226B2 · kind B2 · utility

1Cited by

3References

18Claims

0Family size

Assignee

Arm Limited · GB

Inventors

Gus Yeung · Austin, US
Amarnath Shanmugam · Austin, US
Yew Keong Chong · Austin, US
Jacek Wiatrowski · Ottawa, CA

Key dates

Filing date	Dec 22, 2009
Grant date	Sep 6, 2011
Priority date	—
Expiry date	Dec 31, 2029

Classification

Technology area (CPC G)Physics
CPC primaryG11C8/08
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

An integrated circuit memory 2 incorporates a first array of bit cells 4 and a second array of bit cells 6 with word line driver circuitry 8 disposed therebetween. Word line helper circuitry 18, 20 is disposed at the opposite edges of the array 4, 6 to the word line driver circuitry 8. The helper circuitry is responsive to the word line signal on a word line 12 being driven towards an asserted value to switch on and further drive the word line signal towards the asserted value. The helper circuitry is switched off by a global reset signal, which may be a self-timed global reset signal.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.