Data transfer coherency device and methods thereof
US8015329B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 7, 2010 |
| Grant date | Sep 6, 2011 |
| Priority date | — |
| Expiry date | May 7, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4221
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and a device for performing coherent access requests are disclosed. The methods include receiving a first address associated with a first write or read request. During a write operation, if the first address is associated with a coherent access register, data to be written is stored at a data latch that is connected to a plurality of coherent data access registers. A second address and second data associated with a second write request are received. If the second address matches the first address, the second data and the latched first data are written to the coherent access register. By latching the first data and simultaneously writing the latched first data and the second data, overall coherency of the written data is maintained.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.