Power reduction techniques for components in integrated circuits
US8015425B1 · kind B1 · utility
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13Claims
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Key dates
| Filing date | Aug 5, 2009 |
| Grant date | Sep 6, 2011 |
| Priority date | — |
| Expiry date | Oct 8, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Optimizing the power used in an integrated circuit. A circuit-level transformation/permutation reduces the power consumed by multipliers or other components in integrated circuits. Signals that toggle frequently are assigned to lower power multiplier ports or the number of times a signal changes value is minimized. Large width signals are assigned to the low power port. Large multipliers are divided up and optimized as above. Pipelined multipliers are used with registers so that signals change together.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.