Patent · US Active

Memory circuit

US8015438B2 · kind B2 · utility

16Cited by

5References

21Claims

0Family size

Assignee

Qimonda AG · DE

Inventors

Michael Bruennert · Munich, DE
Christoph Bilger · Munich, DE
Peter Gregorius · Munich, DE
Maurizio Skerlj · Munich, DE
Wolfgang Walthes · Munich, DE
Johannes Stecker · Birkenfeld, DE
Hermann Ruckerbauer · Radolfzell, DE
Dirk Scheideler · Munich, DE
Roland Barth · Schreiber, CA

Key dates

Filing date	Nov 29, 2007
Grant date	Sep 6, 2011
Priority date	—
Expiry date	Jan 9, 2030

Classification

Technology area (CPC G)Physics
CPC primaryG11C2229/726
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

The invention provides a memory circuit comprising a plurality of storage cells for storing data and redundant spare storage cells for replacing defective storage cells, and a memory access logic for accessing said storage cells connected to a replacement setting register which is writeable during operation of said memory circuit to store replacement settings.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.