Preventing livelocks in processor selection of load requests
US8015565B2 · kind B2 · utility
1Cited by
8References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 21, 2005 |
| Grant date | Sep 6, 2011 |
| Priority date | — |
| Expiry date | Nov 1, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/524
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method, and apparatus are provided for preventing livelocks in processor selection of load requests in a multiprocessor (MP) system. On random occasions a selection mechanism is changed for first holding up all requests and then a random selection is made. Then a round robin selection mechanism is used for further requests. A livelock-preventing selection mechanism includes a pair of linear feedback shift registers (LFSRs), each LFSR for generating pseudo random values.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.