Advanced processor with mechanism for packet distribution at high line rate
US8015567B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 31, 2004 |
| Grant date | Sep 6, 2011 |
| Priority date | — |
| Expiry date | Jul 3, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0813
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.