Method of fabricating low on-resistance lateral double-diffused MOS device
US8017486B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 22, 2007 |
| Grant date | Sep 13, 2011 |
| Priority date | — |
| Expiry date | Apr 22, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/516
Abstract
A lateral-double diffused MOS device is provided. The device includes: a first well having a first conductive type and a second well having a second conductive type disposed in a substrate and adjacent to each other; a drain and a source regions having the first conductive type disposed in the first and the second wells, respectively; a field oxide layer (FOX) disposed on the first well between the source and the drain regions; a gate conductive layer disposed over the second well between the source and the drain regions extending to the FOX; a gate dielectric layer between the substrate and the gate conductive layer; a doped region having the first conductive type in the first well below a portion of the gate conductive layer and the FOX connecting to the drain region. A channel region is defined in the second well between the doped region and the source region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.