Electrostatic discharge protection pattern for high voltage applications
US8018000B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 11, 2008 |
| Grant date | Sep 13, 2011 |
| Priority date | — |
| Expiry date | Feb 2, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/516
Abstract
Electrostatic discharge (ESD) protection in high voltage semiconductor devices is disclosed that provides enhanced current isolation between transistor drains or sources by creating an isolation island surrounding the drains or sources. This isolation island can be a higher-doped region within which the drain/source lies. The junction between the higher doping of this island region and the surrounding substrates operates to limit the amount of current that passes through the drain/source. Additionally, oxide features may be used to create an island surrounding the drain/source contact. Again, this isolating effect makes the amount of current passing through the device more uniform, which protects the device from damage due to an ESD event.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.