Semiconductor chip with seal ring and sacrificial corner pattern
US8018030B2 · kind B2 · utility
4Cited by
3References
36Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 24, 2009 |
| Grant date | Sep 13, 2011 |
| Priority date | — |
| Expiry date | Aug 21, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device according to the invention is a semiconductor device which includes a low dielectric constant film of which the relative dielectric constant is less than 3.5, is provided with one or more seal rings that are moisture blocking walls in closed loop form in a plan view, and where at least one of the seal rings includes a seal ring protrusion portion in inward protruding form in the vicinity of a chip corner.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.