Semiconductor die package including multiple semiconductor dice
US8018054B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 12, 2008 |
| Grant date | Sep 13, 2011 |
| Priority date | — |
| Expiry date | Oct 19, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor die package. The semiconductor die package includes a leadframe structure comprising a first die attach pad, and a second die attach pad laterally spaced from the first die attach pad, a first side and a second side opposite to the first side. The semiconductor die package further includes a first semiconductor die attached the first die attach pad at the first side of the leadframe structure, and a second semiconductor die attached to the second die attach pad at the second side of the leadframe structure. The semiconductor die package further includes a housing material covering at least a portion of the leadframe structure, the first semiconductor die, and the second semiconductor die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.