Integrated circuit hard mask processing system
US8018061B2 · kind B2 · utility
0Cited by
5References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 25, 2009 |
| Grant date | Sep 13, 2011 |
| Priority date | — |
| Expiry date | Sep 25, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76835
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit processing system is provided including a substrate having an integrated circuit; an interconnect layer over the integrated circuit; a low-K dielectric layer over the interconnect layer; a hard mask layer over the low-K dielectric layer; a via opening through the hard mask layer and the low-K dielectric layer to the interconnect layer; and an interconnect metal in the via opening.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.