Array of non-volatile memory cells including embedded local and global reference cells and system
US8018773B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 4, 2009 |
| Grant date | Sep 13, 2011 |
| Priority date | — |
| Expiry date | Aug 8, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An array of memory cells has a first side adjacent to a first column, a second side opposite the first side, a third side adjacent to a first row, and a fourth side opposite the third side. Each memory cell is connected to a bit line, a high voltage source, and a low voltage source. Reference cells, substantially the same as the memory cells, evenly spaced apart, are embedded in the array. A high voltage decoder is on the first side, connected to the memory cells and reference cells in the same row. A low voltage row decoder is on the second side, connected to the memory cells and reference cells in the same row. Sense amplifiers are on the third side, connected to the memory cells and to the reference cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.