Memory channel with bit lane fail-over
US8020056B2 · kind B2 · utility
4Cited by
52References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 15, 2010 |
| Grant date | Sep 13, 2011 |
| Priority date | — |
| Expiry date | Jul 15, 2030 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory apparatus and methods utilizing multiple bit lanes may redirect one or more signals on the bit lanes. A memory agent may include a redrive circuit having a plurality of bit lanes, a memory device or interface, and a fail-over circuit coupled between the plurality of bit lanes and the memory device or interface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.