Layout quality gauge for integrated circuit design
US8020120B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 1, 2007 |
| Grant date | Sep 13, 2011 |
| Priority date | — |
| Expiry date | Mar 9, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for layout design includes steps or acts of: receiving a layout for design of an integrated circuit chip; designing mask shapes for the layout; transmitting the mask shapes to a litho simulator for generating wafer shapes; receiving the wafer shapes; calculating electrically equivalent gate lengths for the wafer shapes; analyzing the gate lengths to check for conformity against a threshold value, wherein the threshold value represents a desired value of electrically equivalent gate lengths; placing markers on the layout at those locations where the gate length violates the threshold value; and generating a histogram of gate lengths for comparing layouts for electrically equivalent gate lengths for layout quality.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.