Integrated circuit system with hierarchical capacitor and method of manufacture thereof
US8021954B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 22, 2009 |
| Grant date | Sep 20, 2011 |
| Priority date | — |
| Expiry date | Mar 16, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacture of an integrated circuit system includes: providing a substrate including front-end-of-line circuitry; forming a first group of metal layers including a first finger and a second finger over the substrate utilizing a first design rule, the first group of metal layers being formed without a finger via; forming a second group of metal layers including a first finger, a second finger, and a finger via over the first group of metal layers utilizing a second design rule that is larger than the first design rule; and interconnecting the first group of metal layers with the second group of metal layers to form a capacitor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.