Patent · US Active

Multi-chip stack package

US8022523B2 · kind B2 · utility

18Cited by

12References

8Claims

0Family size

Assignee

NANYA TECHNOLOGY CORPORATION · TW

Inventors

Jen-Chun Chen · Taipei, TW
Wu-Der Yang · Taoyuan, TW

Key dates

Filing date	Jun 10, 2008
Grant date	Sep 20, 2011
Priority date	—
Expiry date	Apr 10, 2030

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/15184
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A multi-chip stack package comprising a first wiring substrate, a first chip, a second wiring substrate, and a second chip is provided. The first wiring substrate is with a front side and a rear side. The first chip is disposed on the front side of the first wiring substrate and electrically connected to the first wiring substrate and the first chip has a first active surface. The second wiring substrate is disposed on the first active surface of the first chip and electrically connected to the first wiring substrate. The second chip is disposed on the second wiring substrate and electrically connected to the second wiring layer. The second active surface of the second chip faces the first active surface of the first chip.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.