Patent · US Active

Overlay mark

US8022560B2 · kind B2 · utility

3Cited by

8References

6Claims

0Family size

Assignee

UNITED MICROELECTRONICS CORP. · TW

Inventors

Min-Hung Chen · Taipei, TW
Kao-Tsair Tsai · Taichung, TW

Key dates

Filing date	Aug 11, 2009
Grant date	Sep 20, 2011
Priority date	—
Expiry date	Aug 28, 2029

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/0002
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

An overlay mark applicable in a non-volatile memory includes two first X-direction isolation structures, two first Y-direction isolation structures, two second X-direction isolation structures, two second Y-direction isolation structures, a first dielectric layer, and a conductive layer. The first X-direction isolation structures, the first Y-direction isolation structures, the second X-direction isolation structures, and the second Y-direction isolation structures are disposed in a substrate. The first X-direction isolation structures and the first Y-direction isolation structures are arranged to a first rectangle, the second X-direction isolation structures and the second Y-direction isolation structures are arranged to a second rectangle, and the second rectangle is located in the first rectangle. The first dielectric layer is disposed on a surface of the substrate. The conductive layer is disposed on the first dielectric layer.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.