Resistive memory devices including selected reference memory cells operating responsive to read operations
US8023311B2 · kind B2 · utility
5Cited by
20References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 23, 2009 |
| Grant date | Sep 20, 2011 |
| Priority date | — |
| Expiry date | Sep 16, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/79
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A Resistance based Random Access Memory (ReRAM) can include a sense amplifier circuit that includes a first input coupled to a bit line of a reference cell in a first block of the ReRAM responsive to a read operation to a second block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.