Method and apparatus for testing a memory device
US8023348B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 29, 2007 |
| Grant date | Sep 20, 2011 |
| Priority date | — |
| Expiry date | Dec 16, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1202
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques for testing a semiconductor memory device are provided. The memory device includes a plurality of memory cells and a plurality of row lines and column lines connected to the memory cells for selectively accessing one or more of the memory cells. The method includes the steps of: applying a first voltage to at least a given one of the row lines corresponding to at least a given one of the memory cells to be tested, the first voltage being selected to stress at least one performance characteristic of the memory device, the first voltage being different than a second voltage applied to the given one of the row lines for accessing at least one of the memory cells during normal operation of the memory device; exercising the memory device in accordance with prescribed testing parameters; and identifying whether the memory device is operable within prescribed margins of the testing parameters.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.