Semiconductor storage device
US8023352B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 9, 2010 |
| Grant date | Sep 20, 2011 |
| Priority date | — |
| Expiry date | Feb 9, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a 4F2 memory cell designed using an SGT as a vertical transistor, a bit line has a high resistance because it is comprised of a diffusion layer underneath a pillar-shaped silicon layer, which causes a problem of slowdown in memory operation speed. The present invention provides a semiconductor storage device comprising an SGT-based 4F2 memory cell, wherein a bit line-backing cell having the same structure as that of a memory cell is inserted into a memory cell array to allow a first bit line composed of a diffusion layer to be backed with a low-resistance second bit line through the bit line backing cell, so as to provide a substantially low-resistance bit line, while suppressing an increase in area of the memory cell array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.