System and method for providing a non-power-of-two burst length in a memory system
US8023358B2 · kind B2 · utility
7Cited by
10References
20Claims
0Family size
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Key dates
| Filing date | Apr 2, 2008 |
| Grant date | Sep 20, 2011 |
| Priority date | — |
| Expiry date | Feb 7, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1018
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system, memory interface device and method for a non-power-of-two burst length are provided. The memory system includes a plurality of memory devices with non-power-of-two burst length logic and a memory interface device including non-power-of-two burst length generation logic. The non-power-of-two burst length generation logic extends a burst length from a power-of-two value to insert an error-detecting code in a burst on data lines between the memory interface device and the plurality of memory devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.