Receiver dynamically switching to pseudo differential mode for SOC spur reduction
US8023919B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 8, 2008 |
| Grant date | Sep 20, 2011 |
| Priority date | — |
| Expiry date | Feb 24, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B15/06
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A low noise amplifier in an integrated circuit, the circuit having a digital portion and an analog portion on a common substrate, the digital portion having at least one clocking frequency, includes an input configured to receive a signal at a tuned frequency and an output circuit. The output circuit is configurable to operate in either a single-ended mode or a pseudo differential-ended mode, wherein the output circuit is configured in the pseudo differential-ended mode when the tuned frequency is substantially similar to the at least one clocking frequency or one of its harmonics and otherwise configured in the single-ended mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.