Method of and apparatus for reducing power consumption within an integrated circuit
US8024591B2 · kind B2 · utility
31Cited by
5References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 10, 2008 |
| Grant date | Sep 20, 2011 |
| Priority date | — |
| Expiry date | Feb 17, 2030 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit comprising a plurality of processing cores, characterised by comprising electrically controllable switches for controlling the supply of power to one or more of the processing cores, a memory for saving state data from at least one of the processing cores and a controller adapted to control the supply of power to one or more of the processing cores such that processing cores can be de-powered.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.