Input/output compression and pin reduction in an integrated circuit
US8024629B2 · kind B2 · utility
5Cited by
27References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 26, 2010 |
| Grant date | Sep 20, 2011 |
| Priority date | — |
| Expiry date | Apr 26, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/3202
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An I/O compression apparatus, for testing a memory array and/or a logic circuit, is comprised of a selectable compression circuit that outputs compressed test data from the memory array/logic circuit. An I/O scan register is coupled to each I/O pad for converting serial data to parallel and parallel data to serial in response to a test mode select signal, a test data input, and a test clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.