Congestion optimization during synthesis
US8024693B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 4, 2008 |
| Grant date | Sep 20, 2011 |
| Priority date | — |
| Expiry date | Oct 22, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/394
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
One embodiment of the present invention provides a system that optimizes a circuit design during a logic design stage to reduce routing congestion during a placement and routing stage. During operation, this system identifies a first circuit structure in the circuit design which is expected to cause routing congestion during the placement and routing stage. Next, the system generates a second circuit structure which is functionally equivalent to the first circuit structure, and is not expected to cause routing congestion during the placement and routing stage. The system then replaces the first circuit structure in the circuit design with the second circuit structure, thereby mitigating routing congestion during the placement and routing stage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.