Tunnel field effect transistor and method of manufacturing same

US8026509B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Niti Goel · Portland, US
• Wilman Tsai · Saratoga, US
• Jack T. Kavalieros · Portland, US

Key dates

• Filing date: Dec 30, 2008
• Grant date: Sep 27, 2011
• Expiry date: Jul 24, 2029

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/824

Abstract

A TFET includes a source region (110, 210), a drain region (120, 220), a channel region (130, 230) between the source region and the drain region, and a gate region (140, 240) adjacent to the channel region. The source region contains a first compound semiconductor including a first Group III material and a first Group V material, and the channel region contains a second compound semiconductor including a second Group III material and a second Group V material. The drain region may contain a third compound semiconductor including a third Group III material and a third Group V material.