Phase locked loop circuit, method of operating phase locked loop circuit and semiconductor memory device including phase locked loop circuit
US8026749B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 18, 2009 |
| Grant date | Sep 27, 2011 |
| Priority date | — |
| Expiry date | Nov 18, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0891
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase locked loop circuit includes a delay compensation circuit and a phase change circuit. The delay compensation circuit is adapted to generate a delay clock signal by delaying a phase of a first output clock signal by a second phase, the phase of the first output clock signal having a phase leading a phase of an input clock signal by a first phase, and the second phase corresponding to a delay compensation time greater than a period of the input clock signal and greater than the first phase. The phase change circuit is adapted to change the second phase to the first phase and to generate a feedback clock signal having a phase synchronized with the phase of the input clock signal in response to the first phase, wherein the first phase is a phase corresponding to a remainder time resulting from the delay compensation time being divided by the period of the input clock, and wherein the quotient is an integer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.