Processor instruction cache with dual-read modes
US8027218B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 2, 2008 |
| Grant date | Sep 27, 2011 |
| Priority date | — |
| Expiry date | Sep 16, 2029 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor includes a cache memory that has an array, word lines, and bit lines. A control module accesses cells of the array during access cycles to access instructions stored in the cache memory. The control module performs one of a first discrete read and a first sequential read to access instructions in a first set of cells of the array that are connected to a first word line and selectively performs one of a second discrete read and a second sequential read based on a branch instruction to access instructions in a second set of cells of the array that are connected to a second word line. The second word line is different than the first word line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.