Method and apparatus for transmitting memory pre-fetch commands on a bus
US8028143B2 · kind B2 · utility
0Cited by
5References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 27, 2004 |
| Grant date | Sep 27, 2011 |
| Priority date | — |
| Expiry date | Apr 18, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/161
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing system and method is disclosed wherein a processor may be configured to predict an address of memory from which data will be needed, transmit to a memory controller a pre-fetch command for the data at the predicted address of the memory, and transmit to the memory controller a read request for the data at the predicted address of the memory if the data is needed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.