Embedded parity coding for data storage
US8028216B1 · kind B1 · utility
33Cited by
6References
54Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 1, 2007 |
| Grant date | Sep 27, 2011 |
| Priority date | — |
| Expiry date | Jul 18, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/1515
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An encoder system includes a receive module that receives a data stream. A parity generation module generates parity bits based on the data stream and a tensor-product code. A parity insertion module combines the parity bits and the data stream to generate encoded bits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.