Multiple-core processor supporting multiple instruction set architectures
US8028290B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 30, 2006 |
| Grant date | Sep 27, 2011 |
| Priority date | — |
| Expiry date | Feb 26, 2027 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Multiple instruction set architectures are supported in a system that provides a power-efficient and flexible platform for virtual machine environments requiring multiple support for multiple instruction set architectures (ISAs). A processor includes multiple cores having disparate native ISAs and that may be selectively enabled for operation, so that power is conserved when support for a particular ISA is not required of the processor. A hypervisor controls operation of the cores, locates a core and enables it if necessary when a request to instantiate a virtual machine having a specified ISA is received. The ISA may be specified by a particular operating system and/or application program requirements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.