Inventor · Red Hook, NY, US

Michael Ignatowski

51Patents
12h-index
61Co-inventors
87Inventor score

Filing activity: Apr 3, 1991 → Feb 8, 2024

Most-cited inventions

PatentTitleAreaCited byStatus
US5895487A Integrated processing and L2 DRAM cache Emerging Cross-Sectional Technologies 127 Expired
US5265232A Coherence control by data invalidation in selected processor caches without broadcasting to processor caches not having the data Physics 96 Expired
US5875470A Multi-port multiple-simultaneous-access DRAM chip Physics 89 Expired
US6457100B1 Scaleable shared-memory multi-processor computer system having repetitive chip structure with efficient busing and coherence controls Physics 80 Expired
US9135185B2 Die-stacked memory device providing data translation Electricity 68 Active
US8028290B2 Multiple-core processor supporting multiple instruction set architectures Emerging Cross-Sectional Technologies 48 Active
US8922243B2 Die-stacked memory device with reconfigurable logic Emerging Cross-Sectional Technologies 44 Active
US7401240B2 Method for dynamically managing power in microprocessor chips according to present processing demands Emerging Cross-Sectional Technologies 36 Expired
US9344091B2 Die-stacked memory device with reconfigurable logic Emerging Cross-Sectional Technologies 23 Active
US9697147B2 Stacked memory device with metadata management Emerging Cross-Sectional Technologies 16 Active
US9201777B2 Quality of service support using stacked memory device with logic die Electricity 15 Active
US9170948B2 Cache coherency using die-stacked memory device with logic die Emerging Cross-Sectional Technologies 15 Active
US7668096B2 Apparatus for modeling queueing systems with highly variable traffic arrival rates Electricity 10 Active
US6768968B2 Method and system of an integrated simulation tool using business patterns and scripts Emerging Cross-Sectional Technologies 9 Expired
US8806182B2 Multiple-core processor supporting multiple instruction set architectures Emerging Cross-Sectional Technologies 8 Active
US7099816B2 Method, system and article of manufacture for an analytic modeling technique for handling multiple objectives Physics 7 Expired
US7484043B2 Multiprocessor system with dynamic cache coherency regions Physics 6 Expired
US9804996B2 Computation memory operations in a logic layer of a stacked memory Emerging Cross-Sectional Technologies 4 Active
US7376083B2 Apparatus and method for modeling queueing systems with highly variable traffic arrival rates Electricity 4 Active
US8122216B2 Systems and methods for masking latency of memory reorganization work in a compressed memory system Physics 4 Active
US9727241B2 Memory page access detection Physics 3 Active
US7647519B2 System and computer program product for dynamically managing power in microprocessor chips according to present processing demands Emerging Cross-Sectional Technologies 3 Active
US9535627B2 Latency-aware memory control Emerging Cross-Sectional Technologies 2 Active
US10482043B2 Nondeterministic memory access requests to non-volatile memory Physics 2 Active
US10817422B2 Data processing system with decoupled data operations Physics 1 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.