Gate electrode for a nonvolatile memory cell
US8030161B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 15, 2008 |
| Grant date | Oct 4, 2011 |
| Priority date | — |
| Expiry date | Dec 10, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/037
Abstract
A nonvolatile memory cell includes a substrate comprising a source, drain, and channel between the source and the drain. A tunnel dielectric layer overlies the channel, and a localized charge storage layer is disposed between the tunnel dielectric layer and a control dielectric layer. A gate electrode has a first surface adjacent to the control dielectric layer, and the first surface includes a midsection and two edge portions. According to one embodiment, the midsection defines a plane, and at least one edge portion extends away from the plane. Preferably, the edge portion extending away from the plane converges toward an opposing second surface of the gate electrode. According to another embodiment, the gate electrode of the nonvolatile memory cell includes a first sublayer and a second sublayer of a different width on the first sublayer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.