Patent · US Active

Methods of forming isolation structures, and methods of forming nonvolatile memory

US8030170B2 · kind B2 · utility

2Cited by

4References

16Claims

0Family size

Assignee

Micron Technology, Inc. · US

Inventors

Yunjun Ho · Boise, US
Matt Meyers · Boise, US
Kevin L. Beaman · Boise, US
Gregory J. Light · Boise, US

Key dates

Filing date	Dec 8, 2009
Grant date	Oct 4, 2011
Priority date	—
Expiry date	Jan 27, 2030

Classification

Technology area (CPC H)Electricity
CPC primaryH10D64/035
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

Some embodiments include methods of forming isolation structures. A trench may be formed to extend into a semiconductor material. Polysilazane may be formed within the trench, and then exposed to steam. A maximum temperature of the polysilazane during the steam exposure may be less than or equal to about 500° C. The steam exposure may convert all of the polysilazane to silicon oxide. The silicon oxide may be annealed under an inert atmosphere. A maximum temperature of the silicon oxide during the annealing may be from about 700° C. to about 1000° C. In some embodiments, the isolation structures are utilized to isolate nonvolatile memory components from one another.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.