Nonvolatile memory device
US8030698B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 8, 2009 |
| Grant date | Oct 4, 2011 |
| Priority date | — |
| Expiry date | Mar 27, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/20
Abstract
Provided is a nonvolatile memory device having a three dimensional structure. The nonvolatile memory device includes a plurality of stacked semiconductor layers and a plurality of memory cell transistors which is formed on each of a plurality of semiconductor layers and serially connected. Memory cell transistors disposed on different semiconductor layers are serially connected to include one cell string forming a current path in a plurality of semiconductor layers, a first selection transistor serially connected to one edge portion of the cell string and a second selection transistor serially connected to the other edge portion of the cell string.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.