Mold design and semiconductor package
US8030761B2 · kind B2 · utility
2Cited by
5References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 23, 2008 |
| Grant date | Oct 4, 2011 |
| Priority date | — |
| Expiry date | Oct 4, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/351
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A chip package includes a carrier having a first and a second major surface. The first major surface includes an active region surrounded by an inactive region. The chip package includes contact pads in the active region for mating with chip contacts of a chip. A support structure is disposed on the inactive region of the first major surface. The support structure forms a dam that surrounds the active region. When a chip or chip stack is mounted in the active region, spacing exists between the dam and the chip or chip stack. The spacing creates convention paths for heat dissipation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.