Resistance change memory device
US8031508B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 7, 2008 |
| Grant date | Oct 4, 2011 |
| Priority date | — |
| Expiry date | Dec 30, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/72
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A resistance change memory device includes: a memory cell array with memory cells arranged therein, the memory cell having a variable resistance element for storing a rewritable resistance value; a reference cell formed of the same memory cells as those set in a high resistance state in the memory cell array, the reference cell being trimmed with selection of the number of parallel-connected memory cells to have a reference current value used for detecting data in the memory cell array; and a sense amplifier configured to compare a cell current value of a memory cell selected in the memory cell array with the reference current value of the reference cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.