Patent · US Active

Memory device and memory system comprising a memory device and a memory control device

US8031539B2 · kind B2 · utility

20Cited by

4References

24Claims

0Family size

Assignee

Qimonda AG · DE

Inventor

Peter Gregorius · Munich, DE

Key dates

Filing date	Oct 9, 2008
Grant date	Oct 4, 2011
Priority date	—
Expiry date	Sep 26, 2029

Classification

Technology area (CPC G)Physics
CPC primaryG11C11/4076
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

In an embodiment, a memory device comprises a clock generating unit being configured to generate a read clock signal, the clock generating unit being connected to a first clock signal contact configured to send the read clock signal, and the clock generating unit being connected to data signal contacts being configured to send data signals, the memory device being configured to send the data signals in a phase and frequency accurate (source synchronous) manner with regard to the read clock signal.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.