Methods of forming recessed gate electrodes having covered layer interfaces
US8034701B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 31, 2009 |
| Grant date | Oct 11, 2011 |
| Priority date | — |
| Expiry date | Jul 31, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/691
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of forming a gate electrode can be provided by forming a trench in a substrate, conformally forming a polysilicon layer to provide a polysilicon conformal layer in the trench defining a recess surrounded by the polysilicon conformal layer, wherein the polysilicon conformal layer is formed to extend upwardly from a surface of the substrate to have a protrusion and the protrusion has a vertical outer sidewall adjacent the surface of the substrate, forming a tungsten layer in the recess to form an upper surface that includes an interface between the polysilicon conformal layer and the tungsten layer, and forming a capping layer being in direct contact with top surfaces of the polysilicon conformal layer and the tungsten layer without any intervening layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.