Semiconductor device including a plurality of memory cells with no difference in erasing properties
US8035154B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 4, 2008 |
| Grant date | Oct 11, 2011 |
| Priority date | — |
| Expiry date | Mar 31, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/201
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a semiconductor substrate, a plurality of memory cells, a plurality of bit lines, and a plurality of source lines. The memory cells are located in the semiconductor substrate. Each of the memory cells includes a trench provided in the semiconductor substrate, an oxide layer disposed on a sidewall of the trench, a tunnel oxide layer disposed at a bottom portion of the trench, a floating gate disposed in the trench so as to be surrounded by the oxide layer and the tunnel oxide layer, and an erasing electrode disposed on an opposing side of the tunnel oxide layer from the floating gate. The bit lines and the source lines are alternately arranged on the memory cells in parallel with each other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.