Semiconductor device with suppressed crystal defects in active areas
US8035169B2 · kind B2 · utility
14Cited by
6References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2008 |
| Grant date | Oct 11, 2011 |
| Priority date | — |
| Expiry date | Jun 30, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/603
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A technique that makes it possible to suppress a crystal defect produced in an active area and thereby reduce the fraction defective of semiconductor devices is provided. A first embodiment relates to the planar configuration of SRAM. One of the features of the first embodiment is as illustrated in FIG. 4. That is, on the precondition that the active areas in n-channel MISFET formation regions are all configured in the isolated structure: the width of the terminal sections is made larger than the width of the central parts of the active areas. For example, the terminal sections are formed in an L shape.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.