Methods of counter-doping collector regions in bipolar transistors
US8035196B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 2, 2008 |
| Grant date | Oct 11, 2011 |
| Priority date | — |
| Expiry date | Apr 1, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/137
Abstract
The present invention provides a method of forming a bipolar transistor. The method includes doping a silicon layer with a first type of dopant and performing a first implant process to implant dopant of a second type opposite the first type in the silicon layer. The implanted dopant has a first dopant profile in the silicon layer. The method also includes performing a second implant process to implant additional dopant of the second type in the silicon layer. The additional implanted dopant has a second dopant profile in the silicon layer different than the first dopant profile. The method further includes growing an insulating layer formed over the silicon layer by consuming a portion of the silicon layer and the first type of dopant.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.