Through wafer via and method of making same
US8035198B2 · kind B2 · utility
15Cited by
13References
30Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 8, 2008 |
| Grant date | Oct 11, 2011 |
| Priority date | — |
| Expiry date | May 5, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A through wafer via structure. The structure includes: a semiconductor substrate having a top surface and an opposite bottom surface; and an array of through wafer vias comprising at least one electrically conductive through wafer via and at least one electrically non-conductive through wafer via, each through wafer via of the array of through wafer vias extending from the top surface of the substrate to between greater than halfway to and all the way to the bottom surface of the substrate. Also methods for fabricating the though wafer via structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.