Delay locked loop and delay locking method having burst tracking scheme
US8035431B2 · kind B2 · utility
3Cited by
3References
12Claims
0Family size
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Key dates
| Filing date | Jun 30, 2009 |
| Grant date | Oct 11, 2011 |
| Priority date | — |
| Expiry date | Nov 14, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/093
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A Delay Locked Loop (DLL) includes a replica delay unit configured to delay an output clock to generate a feedback clock; a phase detector configured to measure a phase difference between the feedback clock and an input clock; a quantization unit configured to quantize the phase difference measured by the phase detector; and a delay unit configured to delay the input clock based on a quantization result from the quantization unit to generate the output clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.