Patent · US Active

Single-event upset immune static random access memory cell circuit

US8036023B2 · kind B2 · utility

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24References

2Claims

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Assignee

BAE Systems Information and Electronic Systems Integration Inc. · US

Inventors

Reed K. Lawrence · Purcellville, US
Nadim F. Haddad · Oakton, US

Key dates

Filing date	Oct 7, 2010
Grant date	Oct 11, 2011
Priority date	—
Expiry date	Oct 7, 2030

Classification

Technology area (CPC G)Physics
CPC primaryG11C11/4125
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A circuit and method are provided in which a six-transistor (6-T) SRAM memory cell is hardened to single-event upsets by adding isolation-field effect transistors (“iso-fets”) connected between the reference voltage Vdd and the field-effect transistors (“fets”) respectively corresponding to first and second inverters of the memory cell. According to certain embodiments, the control gates of first and second P-iso-fets are respectively tied to the control gates of first and second pull-up P-fets. According to certain embodiments, first and second N-iso-fets are connected between the output nodes of the memory cell and the pull-down N-fets respectively corresponding to the first and second inverters. The control gates of the first and second N-iso-fets are respectively tied to the control gates of the first and second pull-down N-fets. Again according to certain embodiments, one or more of the iso-fets are physically removed from the proximity of other transistors which comprise the memory cell.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.