Method and apparatus of high speed encryption and decryption
US8036377B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 12, 2007 |
| Grant date | Oct 11, 2011 |
| Priority date | — |
| Expiry date | Aug 2, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2209/24
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The disclosure provides a hardware architecture for encryption and decryption device. The hardware architecture can improve the encryption and decryption data rate by using parallel processing, and pipeline operation. Further, the hardware architecture can save footprint by sharing hardware components. Additionally, the hardware architecture can be associated with a memory to protect the information stored at the memory. The encryption device can include a tweaking value manager that is configured to generate an array of tweaking values corresponding to the array of data blocks based on a tweaking encryption key, a first encryption unit that is configured to encrypt a first portion of the array of data blocks into a first portion of encrypted data blocks based on corresponding tweaking values and a data encryption key, a second encryption unit that is configured to encrypt a second portion of the array of data blocks into a second portion of encrypted data blocks based on corresponding tweaking values and the data encryption key, and a data block combiner that is configured to combine the first portion of encrypted data blocks and the second portion of encrypted data blocks into an…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.