Spread spectrum clock generation
US8037336B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 15, 2007 |
| Grant date | Oct 11, 2011 |
| Priority date | — |
| Expiry date | Jan 25, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M7/3026
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides a spread spectrum clock generation system having a digitally controlled phase locked loop (PLL) and a digital frequency profile generator to create a near optimal frequency modulation profile for the purpose of achieving spectral flatness in the output frequency modulated clock. The circuit is combined with a multilevel error feedback noise shaping structure that provides the required noise transfer function for the quantization noise but maintains a unity gain all pass signal transfer function. This arrangement offers minimal degradation of the in-band signal-to-noise ratio (SNR) at the cost of higher out-of-band noise.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.