Issuing instructions in-order in an out-of-order processor using false dependencies
US8037366B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 24, 2009 |
| Grant date | Oct 11, 2011 |
| Priority date | — |
| Expiry date | Oct 28, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/0721
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A mechanism is provided for issuing instructions. An instruction dispatch unit receives an instruction for dispatch to one of a plurality of execution units. The instruction dispatch unit analyzes a tag register to determine whether a previous tag associated with a previous instruction has been stored in the tag register. Responsive to the previous tag associated with the previous instruction failing to be stored in the tag register, the instruction dispatch unit storing a tag corresponding to the instruction in the tag register. The instruction dispatch unit dispatches the instruction to an issue queue for issue to the one of the plurality of execution units.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.