Framework for parallelizing general reduction
US8037462B2 · kind B2 · utility
6Cited by
4References
10Claims
0Family size
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Key dates
| Filing date | Aug 2, 2006 |
| Grant date | Oct 11, 2011 |
| Priority date | — |
| Expiry date | Feb 23, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F8/452
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for providing parallel processing capabilities including: performing scalar and array privatization analysis via a compiler; checking whether an assignment statement is reducible; recognizing reduction patterns through a pattern matching algorithm; classifying a reduction type of each of the reduction patterns; and performing transformations and code generation for each reduction the reduction type of each of the reduction patterns.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.